In the manufacturing of integrated circuits, photolithography (or lithography) is typically used to transfer patterns related to the layout of an integrated circuit onto a wafer substrate including, but not limited to, materials such as silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), or various combinations thereof. The drive to improve the performance of very-large-scale integrated (VLSI) circuits results in the increasing requirements to decrease the size of components and to increase the density of layouts. This in turn requires the use of resolution-enhancement techniques (RET) to extend the capabilities of optical lithographic processes. RET includes techniques of optical proximity correction (OPC), sub-resolution assist feature (SRAF) enhanced lithography and phase-shifted-mask (PSM) enhanced lithography.
Applications of complex RET techniques have considerably increased the cost of masks and lithographic manufacturing. A computer-based simulation of wafer images thus becomes necessary to verify the pattern transfer capabilities (also referred to as printability) of a mask through the variability of a process before the mask is actually manufactured.
The ever increasing costs of mask manufacturing and inspection and the ever increasing complexity of OPC and RET techniques require that a mask is correctly and accurately simulated to eliminate potential defects before the mask is manufactured. This area is generally known as mask manufacturability verification or mask printability verification. An accurate simulation is the primary focus of printability verification. This means that the printability verification simulation should not miss any real error on the mask. As is appreciated, the cost of a defective mask being actually manufactured and used for chip manufacturing is extremely high. Nevertheless, there are two other important objectives of a printability verification tool. First, a simulation needs to be done as quickly as possible. As the feedback from the printability verification is used for the development of OPC and RET, a fast feedback is desirable to minimize the turn-around time (TAT) for OPC and RET developments. Second, there should be as few “false errors” as possible. A false error is defined as a mask layout error identified by a printability verification process using its simulation tool, which will not happen on a wafer if the mask is actually used in a lithographic process. Since missing a real error is significantly more expensive than identifying a false error, all printability verification tools are expected to err on the conservative side, i.e., tending to detect more errors including false errors. However, since each error, whether false or real, needs to be checked manually, it is desirable that a printability verification tool does not identify too many false errors. If there are too many false errors, the real errors may be overwhelmed and potentially missed in a manual inspection because it would be time consuming to evaluate all the false errors to find the real errors.
Current printability verification methods tend to simulate the whole mask layout image with the most accurate geometry using very conservative criteria. This tends to increase the runtime of the printability verification process along with the number of false errors. For example, the state of the art techniques simulate a mask layout (or a segment thereof) using a calibrated resist and optical model. The simulated image is then compared to the corresponding target shape. If the simulated wafer segment is not within a tolerance of the corresponding target shape, it is reported as problematic, i.e., including an error.
FIG. 1 shows an exemplary mask layout 10 with an exemplary simulated wafer image 16. Mask layout 10 includes a main mask shape(s) 12 and sub resolution assist features (SRAF) 14 that do not print themselves but help in the printing of main mask shapes 12. Simulated wafer image 16 is shown as the patterned shapes, which correspond to main mask shape 12. As shown in FIG. 1, various kinds of errors are included in simulated image 16, wherein:
20 depicts a “necking error”, where the wafer image shape width is smaller than a pre-determined value;
22 depicts a “bridging error”, where the spacing between two wafer image shapes is smaller than a pre-determined value;
24 depicts an “edge placement error”, where the wafer image shape at an edge is divergent from a target edge, as indicated by main mask shape 12, by a predetermined value;
26 depicts an “line end shortening error”, where the wafer image shape at a line-end is divergent from a target line end, as indicated by main mask shape 12, by a predetermined value;
28 depicts an SRAF printing error, where a part of the SRAF is printed; and
30 depicts additional printing errors due to, e.g., diffraction effects of lighting such as side-lobe printing errors.
The printability errors can be categorized into two categories. The errors in the first category are known as the catastrophic errors, because a circuit will fail to function at all if any of these errors occur. The other category of errors is known as the performance errors. Errors of this type do not make the circuit malfunction. But the performance of the circuit in terms of, e.g., the speed or the power consumption may degrade with such errors increasing. Examples of catastrophic errors are: necking errors 20, bridging errors 22, SRAF and additional image (such as side lobe) printing errors 28, 30. On the other hand, edge placement errors 24 are usually considered to be examples of performance errors. Line end shortening errors 26 can be categorized as catastrophic if they happen to miss any connections with the next layer in the chip due to overlay errors. All catastrophic errors in a mask layout must be corrected before the circuit is manufactured using the mask layout. On the other hand, the performance errors are considered statistically, wherein a small amount of performance errors may be tolerated across the mask layout.
The shapes on a designed mask layout (hereinafter referred to as a mask) are typically defined as/represented by polygons. For simulation purposes, the edges of each mask shape can be divided into smaller line segments. At the heart of a printability verification tool is a simulator that simulates the image intensity at a particular point, which is typically, but not necessarily, at the center of each of the line segments. While the accuracy of the verification may improve as the number of segments increases, the efficiency of a verification tool may decrease.
The segmentation of the mask shape depends on the number of edges on a polygon. The position at which an edge prints is influenced by other nearby mask polygons. Large perturbing features have a stronger influence than small features, but in general the interaction will fall off with an increasing separation distance. Partially coherent image formation is a non-linear process such that the falling off in interaction is not a fixed function of distance. However, the general scaling behavior is that of the so-called lens impulse response function, also known as the Airy function. Mathematically, the Airy function is [J1(2π·s)/(π·s)]2, where J1 is the first Bessel function, and s is a dimensionless position coordinate in the image plane, defined as s=x·NA/λ, where x is the position as measured in conventional length units, NA is the effective numerical aperture of the lithographic system, and λ is the wavelength of the illumination light.
Any details in a mask would interact during the fragmentation procedure to create corresponding segmentations on a neighboring mask shape. Some of those fragments may be created by variations of a neighboring shape that is quite far away from the main shape. Some of those distant fragments may have very little impact on the wafer image simulation. Such distant segmentations would eventually contribute to the inefficiency of a printability verification process. This inefficiency is exacerbated by the fact that the further away a neighboring shape is located, the smaller the proximity effects on a particular mask shape. However, the conventional OPC methodologies do not take advantage of the above fact.
Based on the above; there is a need in the art for verifying mask printability in a manner that improves the efficiency of the verification while maintaining the accuracy or effectiveness of the OPC.